Design of Double Gate Vertical MOSFET using Silicon On Insulator (SOI) Technology

Received April 27, 2012 Revised May 14, 2012 Accepted May 26, 2012 Application of symmetric double gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the parasitic overlap capacitance in the double gate vertical MOSFETs by using SOI (Silicon on Insulator) in bottom planar surfaces side. The result shows that while channel length decreases, the threshold voltage goes lower, the DIBL rises and subthreshold swing tends to decrease, for both structures. It is noted that the SOI DG VMOSFET structure generally have better performance in SCE control compared to bulk vertical MOSFET. The presence of buried oxide is believed to increase the performance of vertical MOSFET, essentially in controlling the depletion in subthreshold voltage. Keyword: